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asix electronics corporation frist released date: dec/20/2001 2f, no.13, industry east rd. ii, science-based industrial park, hsin-chu city, taiwan, r.o.c. tel: 886-3-579-9500 fax: 886-3-579-9558 http:// www.asix.com.tw ax88172 l usb to fast ethernet/homepna controller usb to fast ethernet/homepna controller document no.: ax172-4/ v1.4 / dec, 20/02 features ? single chip usb to 10/100mbps fast ethernet and 1/10mbps homepna and homeplug network controller ? compliant with usb specification 1.0 and 1.1 and 2.0 ? full/high speed usb device with bus power capability ? support 4 endpoints on usb ? ieee 802.3u 100base-t, tx, and t4 compatible ? embedded 7k*16 bit sram, 256*16 bit sram and 8 fifos ? support both full-duplex or half-duplex operation on fast ethernet ? provides a mii port for both ethernet and homepna/ homeplug phy interface ? supports suspended mode and remote wakeup (link_up or magic packet or external pin) ? optional phy power down mode for power saving ? support (94c56/93c66) 256/512 bytes serial eeprom (used for saving usb descriptors) ? support automatic loading of ethernet id, usb descriptors and adapter configuration from eeprom on power-on initialization ? external phy loop-back diagnostic capability ? small form factor with 80-pin lqfp package ? single 12mhz clock input, pure 3.3v operation *ieee is a registered trademark of the institute of electrical and electronic engineers, inc. *all other trademarks and registered trademark are the property of their respective holders. product description the ax88172 usb to fast ethernet/homepna/homeplug controller is a high performance and highly integrated controller with embedded 7k*16 bit sr am. the ax88172 contains a usb interface to host cpu and compliant with usb standard v1.0, v1.1 and v2.0. the ax88172 could be us ed for both 10m/100mbps fast ethernet function based on ieee802.3 / ieee802.3u lan standard and 1m/10m homepna st andard. the ax88172 supports media-independent interface (mii) to simplify the design on implemen ting fast ethernet a nd homepna functions. system block diagram always contact asix for possible updates before starting a design. this data sheet contains new products information. asix electr onics reserves the rights to m odify product speci fication without notice. no liability is assumed as a result of the us e of this product. no rights under any pa tent accompany the sale of the product. ax88172 10/100 mbps ethernet phy/txrx magnetic rj45 usb i/f eeprom 1/10 mbps home lan phy magnetic rj11
asix electronics corporation 2 ax88172 preliminary contents 1.0 introduction............................................................................................................... ........ 4 1.1 g eneral d escription :............................................................................................................. 4 1.2 ax88172 b lock d iagram :...................................................................................................... 4 1.3 ax88172 p in c onnection d iagram ....................................................................................... 5 2.0 signal description......................................................................................................... .. 6 3.0 eeprom memory mapping............................................................................................ 9 4.0 usb commands ............................................................................................................... .... 11 4.1 usb standard commands .................................................................................................... 11 4.2 usb v endor c ommands ....................................................................................................... 12 5.0 usb configurat ion structure .............................................................................. 14 5.1 usb c onfiguration . ............................................................................................................. 14 5.2 usb i nterface ....................................................................................................................... 14 5.3 usb e ndpoints . ..................................................................................................................... 14 6.0 electrical specifi cation and timings ............................................................ 15 6.1 a bsolute m aximum r atings ............................................................................................... 15 6.2 g eneral o peration c onditions .......................................................................................... 15 6.3 dc c haracteristics ............................................................................................................. 15 6.4 a.c. t iming c haracteristics ............................................................................................... 16 6.4.1 12m_xin .................................................................................................................. ......... 16 6.4.2 reset timing ............................................................................................................. ......... 16 6.4.3 mii timing............................................................................................................... .......... 17 6.4.4 station management timing................................................................................. 18 6.4.5 serial eeprom timing .............................................................................................. 19 7.0 package information.................................................................................................. 20 appendix a: system applications ................................................................................ 21 a.1 usb to f ast e thernet c onverter .................................................................................... 21 a.2 usb to f ast e thernet and / or h ome lan c ombo solution ........................................... 21 demonstration circuit a: ax88172 (ed2 version) + ethernet phy(8201l) ............................................................................................................................... ............................ 22 demonstration circuit b: ax88172 (e d3 version) + ethernet phy (8201lbl) ...................................................................................................................... .................. 24 remark: ........................................................................................................................ ............... 26 revisions history .............................................................................................................. ... 27
asix electronics corporation 3 ax88172 preliminary figures f ig ? 1 ax88172 b lock d iagram ............................................................................................................................... ....4 f ig ? 2 ax88172 p in c onnection d iagram ...................................................................................................................5 tables t ab - 1 pin signals ............................................................................................................................... ...........................8 t ab - 2 eeprom m emory m apping ..............................................................................................................................9
asix electronics corporation 4 ax88172 preliminary 1.0 introduction 1.1 general description: the ax88172 usb to fast ethernet controller is a high performance and highly integrated usb bus ethernet controller with embedded 7k*16 bit sram. the ax88172 supported full/h igh speed usb device with bus power capability. the ax88172 implements both 10mbps and 100m bps ethernet function based on ieee802.3/ i eee802.3u lan standard. the ax88172 supports media-inde pendent interface (mii) to simplify the de sign on implementing fa st ethernet and homepna functions. ax88172 uses 80-pin lqfp low profile package, 12mhz opera tion for usb and 25mhz operation for ethernet, cmos process with pure 3.3v operation. 1.2 ax88172 block diagram: fig ? 1 ax88172 block diagram mac core memory arbiter usb to ethernet bridge usb core and interface sta seeprom loader i/f dm/dp mii /if mdc mdio eecs eeck eedi eedo 7k* 16 sram
asix electronics corporation 5 ax88172 preliminary 1.3 ax88172 pin connection diagram the ax88172 is housed in the 80-pin plastic light quad flat pack. fig ? 2 ax88172 pin connection diagram avdd avss avss avss dp avss dm avdd extwakeupn n c n c vdd mdc mdio n c vdd txd0 txd1 txd2 txd3 txen vdd rxclk rxd0 rxd1 rxd2 rxd3 vdd rxer rxdv test1 gpio2 phyrstn n c nc led vdd nc nc vss eecs eec k eedi eedo vss nc nc ana_xiq vdd clki testmode reset/reset vss vdd pvdd pvss vc xout12m xin12m 80 79 78 77 76 75 74 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 73 72 71 70 69 68 67 66 65 asix ax88172 17 18 19 20 37 38 39 40 44 43 42 41 64 63 62 61 r1 eptest n c n c n c vss vss vdd test0 gpio0 gpio1 vdd rst_type nc nc nc crs txclk vbus col phyrstp ed3
asix electronics corporation 6 ax88172 preliminary 2.0 signal description the following terms describe the ax88172 pin-out: all pin names with the ?/? suffix are asserted low. the following abbreviations are used in following tables. i input pu internal pull up (100k) o output pd internal pull down (100k) i/o input/output p power pin od open drain signal type pin no. description r1 i 1 constant-votage pin a 6.2k 1% resistors is connected to avss. be sure to make the line between r1 and each resistor as short as possible. avdd p 2 power supply pin for analog circuits +3.3v dc avss p 3 power supply pin for analog circuits ground avss p 4 power supply pin for analog circuits ground dp b 5 usb data line data+ avss p 6 power supply pin for analog circuits ground dm b 7 usb data line data- avss p 8 power supply pin for analog circuits ground avdd p 9 power supply pin for analog circuits +3.3v dc /extwakeup i/pu 10 remote-wakeup trigger from external pin. it active low and should be keep low over 2 clocks (12mhz) nc b 11 for testing nc b 12 for testing vdd p 13 power supply for logic circuits: +3.3v dc. mdc o 14 station management data clock: the timing reference for mdio. all data transfers on mdio are synchronized to the rising edge of this clock. mdc is a 2.5mhz frequency clock output. mdio i/o/pu 15 station management data input/output: serial data input/output transfers from/to the phys. the tran sfer protocol conforms to the ieee 802.3u mii specification. nc o 16 for testing nc o 17 for testing nc o 18 for testing nc o 19 for testing vss p 20 power supply: +0v dc or ground power. vdd p 21 power supply for logic circuits: +3.3v dc. col i 22 collision: this signal is driven by phy when collision is detected. nc 23 no connection tx_clk i 24 transmit clock: tx_clk is a continuous clock from phy. it provides the timing reference for the transfer of the tx_en and txd[3:0] signals from the mii port to the phy. crs i 25 carrier sense: asynchronous signal crs is asserted by the phy when either the transmit or receive medium is non-idle. txd[3:0] o 29, 28, 27, 26 transmit data: txd[3:0] is transition synchronously with respect to the rising edge of tx_clk. fo r each tx_clk period in which tx_en is asserted, txd[3:0] ar e accepted for transmission by the phy.
asix electronics corporation 7 ax88172 preliminary tx_en o 30 transmit enable: tx_en is transition synchronously with respect to the rising edge of tx_clk. tx_e n indicates that the port is presenting nibbles on txd [3:0] for transmission. vdd p 31 power supply for logic circuits: +3.3v dc. rx_clk i 32 receive clock: rx_clk is a continuous clock that provides the timing reference for the transfer of the rx_dv, rxd[3:0] and rx_er signals from the phy to the mii port of the mac. rxd[3:0] i 36, 35, 34, 33 receive data: rxd[3:0] is driven by the phy synchronously with respect to rx_clk. vdd p 37 power supply for logic circuits: +3.3v dc. rx_er i 38 receive error: rx_er is driven by phy and synchronous to rx_clk, is asserted for one or more rx_clk periods to indicate to the port that an error has detected. rx_dv i 39 receive data valid: rx_dv is driven by the phy synchronously with respect to rx_clk. asserted high when valid data is present on rxd [3:0]. vss p 40 power supply: +0v dc or ground power. vdd p 41 power supply for logic circuits: +3.3v dc. test0 i/pu 42 test pin: this pin for test purpose only. pull up the pin or keep no connection for normal operation. test1 i/pu 43 test pin: this pin for test purpose only. pull up the pin or keep no connection for normal operation. gpio[2:0] i/o/pu 46, 45, 44 general purpose input/ output pins. /phyrst o 47 output for reset phy active low phyrst o 48 output for reset phy active high vss p 49 power supply: +0v dc or ground power. nc i/pd 50 for testing nc i/pd 51 for testing led o 52 led indicator: when link fs, drives logic high always. when link hs, the pin drives logic low. and it will drives high/low a period when line has activity (data transfer). vdd p 53 power supply for logic circuits: +3.3v dc. nc i/pd 54 for testing nc id 55 for testing eecs o 56 eeprom chip select: eeprom chip select signal. eeck o 57 eeprom clock: signal connected to eeprom clock pin. eedi o 58 eeprom data in: signal connected to eeprom data input pin. eedo i/pd 59 eeprom data out: signal connected to eeprom data output pin. vss p 60 power supply: +0v dc or ground power. vdd p 61 power supply for logic circuits: +3.3v dc. rst_type i/pu 62 this pin define the assert level of reset (pin 72) when =?1? or nc, reset signal is active high when =?0?, reset signal is active low nc i/pd 63, 64, 65, 66, 67 for testing ana_xiq i 68 sets the iq mode this pin is used during testing. it must be set to low in iq measurement mode. 0: iq mode 1: normal operation mode vdd p 69 power supply for logic circuits: +3.3v dc. clki i/pd 70 external 60mhz input testmode i/pd 71 for testing (testmode) 0: normal operation mode 1: external clock synchronization mode
asix electronics corporation 8 ax88172 preliminary reset/reset i 72 reset/reset reset is active high/low depend on rst_type (pin 62) definition. when assert, place ax88172 into re set mode immediately. reset complete loads the eeprom data. vss p 73 power supply: +0v dc or ground power. vdd p 74 power supply for logic circuits: +3.3v dc. pvdd p 75 power supply pin for pll a nd oscillator circuits +3.3v dc pvss p 76 power supply pin for pll and oscillator circuits +0v dc or ground powe vc i 77 monitor pin for two pll charge pumps connect to gnd on pcb when actually using ptest i 78 charge pump monitor on/off: connect to gnd on pcb when actually using xin12m i 79 12m crystal oscillator input xout12m o 80 12m crystal oscillator output tab - 1 pin signals
asix electronics corporation 9 ax88172 preliminary 3.0 eeprom memory mapping eeprom offset high byte low byte 00h reserved word count for preload 01h *flag 02h high-speed length of device descriptor (byte) high-speed eeprom offset of device descriptor 03h high-speed length of configuration descriptor (byte) high-speed eeprom offset of configuration descriptor 04h node id 1 node id 0 05h node id 3 node id 2 06h node id 5 node id 4 07h language id high byte language id low byte 08h length of string index 1 eeprom offset of string index 1 09h length of string index 2 eeprom offset of string index 2 0ah length of string index 3 eeprom offset of string index 3 0bh length of string index 4 eeprom offset of string index 4 0ch length of string index 5 eeprom offset of string index 5 0dh length of string index 6 eeprom offset of string index 6 0eh length of string index 7 eeprom offset of string index 7 0fh reserved reserved 10h max packetsize high byte max packet low byte 11h **(phy type[7:5]) (secondary phy id[4:0]) **(phy type[7:5])(first phy id[4:0] ) 12h pause packet high water level pause packet low water level 13h full-speed length of device descriptor (byte) full-speed eeprom offset of device descriptor 14h full-speed length of configuration descriptor (byte) full-speed eeprom offset of configuration descriptor 15h-1fh reserved reserved tab - 2 eeprom memory mapping note: *flag: bit0 self powered (for usb getstatus) 1: self power ; 0 : bus power bit 1 reserved bit 2 remotewakeup support bit 3 1 bit 4 ?5 reserved bit 6 rx drop crc enable bit 7 tx append crc enable bit 8 capture effective mode bit 9 ? f reserved
asix electronics corporation 10 ax88172 preliminary ** phy type[7:5] 3?b000 = 10/100 ethernet phy or 1m home phy (link report as normal case) 3?b100 = special case 1 (link report always active) 3?b101 = reserved 3?b111 = no supported phy for example: eeprom offset 11 high byte is ?e0? mean is no supported secondary phy. ***unicode mac address: if the mac?s node id is 01,23,45,67,89,abh respect to node id 0, node id 1, ? node id5 then the unicode will be 30-31,32-33,34-35,36-37, 38-39,41-42h respects to byte 1 of unicode mac address- byte 2 of unicode mac address, ?-byte 12 of unicode mac address. isolate 2 phy step procedure by ha rdware when every hardware reset 1. write 0 phy_id isolate and power down 2. write primarily phy id isolate and power down 3. write secondary phy id isolate and power down
asix electronics corporation 11 ax88172 preliminary 4.0 usb commands there are three command groups for endpoint 0 in ax88172: the usb standard commands usb communication class commands usb vendor commands. 4.1 usb standard commands the language id is 0x0904 for english ppll means buffer length cc means configuration number i i means interface number setup command data in/out description 80 06 00 01 00 00 ll pp data ppll bytes get device descriptor 80 06 00 02 00 00 ll pp data ppll bytes get configuration descriptor 80 06 00 03 00 00 ll pp data 2 bytes get supported language id 80 06 01 03 09 04 ll pp data ppll bytes get manufacture string 80 06 02 03 09 04 ll pp data ppll bytes get product string 80 06 03 03 09 04 ll pp data ppll bytes get serial number string 80 06 04 03 09 04 ll pp data ppll bytes get configuration string 80 06 05 03 09 04 ll pp data ppll bytes get interface 0 string 80 06 06 03 09 04 ll pp data ppll bytes get interface 1/0 string 80 06 07 03 09 04 ll pp data ppll bytes get interface 1/1 stirng 80 06 08 03 09 04 ll pp data 12 bytes get ethernet address string 80 08 00 00 00 00 01 00 data 1 bytes get configuration 00 09 cc 00 00 00 00 00 no data set configuration 81 0a 00 00 i i 00 01 00 data 1 byte get interface 01 0b as 00 00 00 00 00 no data set interface tab - 3 usb stabdard commands
asix electronics corporation 12 ax88172 preliminary 4.2 usb vendor commands setup command data in/out description c0 02 xx yy 0m 00 02 00 data 2 bytes read rx/tx sram m = 0 : rx, m=1 : tx 40 03 xx yy pp qq 00 00 no data write rx sram 40 04 xx yy pp qq 00 00 no data write tx sram 40 06 00 00 00 00 00 00 no data software mii operation c0 07 pi 00 rg 00 02 00 data 2 bytes read mii register 40 08 pi 00 rg 00 02 00 data 2 bytes write mii register c0 09 00 00 00 00 01 00 data 1 bytes read mii operation mode 40 0a 00 00 00 00 00 00 no data hardware mii operation c0 0b dr 00 00 00 02 00 data 2 bytes read srom 40 0c dr 00 mm ss 00 00 no data write srom 40 0d 00 00 00 00 00 00 no data write srom enable 40 0e 00 00 00 00 00 00 no data write srom disable c0 0f 00 00 00 00 02 00 data 2 bytes read rx control register 40 10 rr 00 00 00 00 00 no data write rx control register c0 11 00 00 00 00 03 00 data 3 bytes read ipg/ipg1/ipg2 register 40 12 ii 00 00 00 00 00 no data write ipg register 40 13 ii 00 00 00 00 00 no data write ipg1 register 40 14 ii 00 00 00 00 00 no data write ipg2 register c0 15 00 00 00 00 08 00 data 8 bytes read multi-filter array 40 16 00 00 00 00 08 00 data 8 bytes write multi-filter array c0 17 00 00 00 00 06 00 data 6 bytes read node id c0 19 00 00 00 00 02 00 data 2 bytes (*) read ethernet/homepna phyid c0 1a 00 00 00 00 01 00 data 1 byte read medium status (**) 40 1b mm 00 00 00 00 00 no data write medium mode (**) c0 1c 00 00 00 00 01 00 data 1 byte get monitor mode status (***) 40 1d mm 00 00 00 00 00 no data set monitor mode on/off (***) c0 1e 00 00 00 00 01 00 data 1 byte read gpios (****) 40 1f mm 00 00 00 00 00 no data write gpios (****) * note1: read 1 st byte is secondary phy id; 2 nd byte is primarily phy id ** read / write medium status bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 read x x x flow_control_en txabortallow full_duplex write x x x flow_control_en x txabortallow full_duplex x *** read / write monitor mode bit7-5 bit4 bit3 bit2 bit1 bit0 read 3?b101 hs/fs x magic_packet_en link_up_wake monitor_mode write x x x magic_packet_en link_up_wake monitor_mode **** read / write gpio bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 read gpi2 gpo2en gpi1 gpo1en gpi0 gpo0en write gpo2 gpo2en gpo1 gpo1en gpo0 gpo0en
asix electronics corporation 13 ax88172 preliminary interrupt endpoint frame format byte number byte 0 a1 fixed value 00 byte 1 00 fixed value 00 byte 2 nn bit_1: secondary p hy link state (active high), bit_0: primarily phy link state byte 3 00 fixed value 00 byte 4 00 fixed value 00 byte 5 80 90h byte 6 00 fixed value 00 byte 7 00 fixed value
asix electronics corporation 14 ax88172 preliminary 5.0 usb configuration structure 5.1 usb configuration. the ax88172 supports 1 configuration only. 5.2 usb interface. the ax88172 supports 2 interfaces, the interface 0 is data interface and interface 1 is for communication interface. 5.3 usb endpoints. the ax88172 supports 4 endpoints. endpoint 0 control endpoint, it is for configuring device. endpoint 1 (optional) interrupt endpoint, it is for reporting status endpoint 2 bulk out endpoint, it is for transmitting ethernet packet. endpoint 3 bulk in endpoint, it is fo r receiving ethernet packet.
asix electronics corporation 15 ax88172 preliminary 6.0 electrical specification and timings 6.1 absolute maximum ratings description sym min max units operating temperature ta 0 +85 c storage temperature ts -65 +150 c supply voltage vdd -0.3 +3.6 v input voltage vin -0.3 vdd+0.3 v output voltage vout -0.3 vdd+0.3 v lead temperature (soldering 10 seconds maximum) tl -55 +240 c note: stress above those listed under absolute maximum rati ngs may cause permanent damage to the device. exposure to absolute maximum ratings conditions for extended period, adversely affect device life and reliability. 6.2 general operation conditions description sym min tpy max units operating temperature ta 0 25 +70 c supply voltage vdd +3.0 +3.30 +3.6 v 6.3 dc characteristics (vdd=3.0v to 3.6v, vss=0v, ta=0 c to 70 c) description sym min tpy max units low input voltage vil - 0.3*vdd v high input voltage vih 0.7*vdd - v low output voltage vol - 0.4 v high output voltage voh 2.4 - v input leakage current iil -1 +1 ua output leakage current iol -10 +10 ua input pull-up / down resistance ri 75 k ohm description sym min tpy max units power consumption (3.3v) spt3v 150 ma
asix electronics corporation 16 ax88172 preliminary 6.4 a.c. timing characteristics 6.4.1 12m_xin (cl=16pf, +/-50ppm) 12m_xin tr tf tlow symbol description min typ. max units tcyc cycle time 83.33 ns thigh clk high time 34.71 41.66 49.99 ns tlow clk low time 34.71 41.66 49.99 ns tr/tf clk slew rate 1 - 4 ns 6.4.2 reset timing 12m_xin reset/reset symbol description min typ. max units trst reset pulse width (6ms ~10ms) 100 - - 12m _xin tcyc thigh
asix electronics corporation 17 ax88172 preliminary 6.4.3 mii timing ttclk ttch ttcl txclk(in) ttv tth txd<3:0>(out) txen(out) trclk trch trcl rxclk(in) trs trh rxd<3:0>(in) rxdv(in) trs1 rxer(in) crs(in) symbol description min typ. max units ttclk cycle time(100mbps) - 40 - ns ttclk cycle time(10mbps) - 400 - ns ttch high time(100mbps) 14 - 26 ns ttch high time(10mbps) 140 - 260 ns trch low time(100mbps) 14 - 26 ns trch low time(10mbps) 140 - 260 ns ttv clock to data valid 3 - 10 ns tth data output hold time 3 - 10 ns trclk cycle time(100mbps) - 40 - ns trclk cycle time(10mbps) - 400 - ns trch high time(100mbps) 14 - 26 ns trch high time(10mbps) 140 - 260 ns trcl low time(100mbps) 14 - 26 ns trcl low time(10mbps) 140 - 260 ns trs data setup time 6 - - ns trh data hold time 6 - - ns trs1 rxer data setup time 6 - - ns
asix electronics corporation 18 ax88172 preliminary 6.4.4 station management timing mdc mdio (output) mdio (input) symbol description min typ. max units tclk mdc clock cycle time 375 khz tch mdc clock high time 1328 ns tcl mdc clock low time 1328 ns tod clock falling edge to output valid delay 0 2 ns ts data in setup time 10 ns th data in hold time 100 ns to d tclk ts th tch tcl
asix electronics corporation 19 ax88172 preliminary 6.4.5 serial eeprom timing eeck eedi (output) eecs eedo (input) symbol description min typ. max units tclk eeck clock cycle time 187.5 khz tch eeck clock high time 2666 ns tcl eeck clock low time 2666 ns tdv eedi data valid output to eeck high time 2666 ns tod eeck high to eedi data output delay time 2666 ns tscs eecs valid to eeck high time 2666 ns thcs eeck low to eecs invalid time 0 ns tlcs minimum eecs low time 23904 ns ts data input setup time 10 ns th data input hold time 100 ns tch tclk tcl valid valid tdv tod tscs thcs tlcs th data valid ts
asix electronics corporation 20 ax88172 preliminary 7.0 package information b e d hd e he pin 1 a2 a1 l l1 a milimeter symbol min. nom max a1 0.05 0.1 0.15 a2 1.3 1.40 1.5 a 1.70 b 0.175 0.18 0.28 d 11.9 12.00 12.1 e 11.9 12.00 12.1 e 0.5 hd 13.6 14.00 14.4 he 13.6 14.00 14.4 l 0.3 0.50 0.7 l1 1.00 0 10
asix electronics corporation 21 ax88172 preliminary appendix a: system applications some typical applications fo r ax88170 are illustrated bellow. a.1 usb to fast ethernet converter a.2 usb to fast ethernet and/or homelan combo solution ax88172 10/100 phy/txrx magnetic rj45 usb i/f eeprom ax88172 10/100 mbps ethernet phy/txrx magnetic rj45 usb i/f eeprom 1/10 mbps home lan phy magnetic rj11
ax88172 usb to fast ethernet/homepna controller asix electronics corporation 22 demonstration circuit a: ax88172 (ed2 version) + ethernet phy(8201l) ax88172 2.1 ax88172 demo board b 12 friday, may 31, 2002 title size document number rev date: sheet of vdd3 vdd3l vdd3l vdd3 vdd5 vdd3l gnd rxdv vdd3l rxer rxd2 rxd3 txd3 rxd0 vdd3l rxd1 rx_clk txen txd1 crs txd2 txd0 tx_clk vdd3l rst vdd3l vdd3l mdio vdd3l mdc vdd3l col tx_clk mdio rx_clk txen txd0 rxer txd2 mdc col rxd0 vdd3 gnd rxd1 rxd3 rxd2 rxdv txd3 txd1 /phy_rst crs dplus eedo eecs eedi eeck vdd3l gnd gnd dminus gnd /phy_rst eedo eedi eeck eecs vdd3 led vdd3l vdd3 rst vdd3l dminus dplus vdd5 60mhz 60mhz avdd avss vdd3 pvss vdd3 pvdd vdd3 pvdd vdd3 gnd pvss gnd gnd avss avdd avss avdd avss gnd gnd gnd avss c37 0.1u c34 0.1u c32 0.1u c31 0.1u j1 dc power jack 1 2 3 + c20 47u/16v l5 f.bead. + c35 22u c19 0.01u d2 diode c2 0.1u l1 f.bead. u5 ams1117 3 2 1 vin vout adj/gnd + c16 10u/16v c17 0.1u c12 0.1u l2 f.bead. u3 xc74ul14 1 3 4 5 2 nc gnd y vcc a c24 0.1u c3 0.1u c27 0.1u l3 f.bead. u2 93c56 1 2 3 4 5 6 7 8 cs sk di do gnd nc nc vcc c25 0.1u c33 0.01u s1 sw pushbutton c29 0.1u c26 0.1u c22 0.1u + c18 47u/16v c21 0.1u c23 0.1u r9 0 c9 0.1u r6 6.2k 1% c4 0.1u r1 1k d1 led c6 0.1u u4 60mhz 8 4 5 vcc gnd out c15 0.1u c14 0.1u r8 33 + c30 22u c36 0.01u c11 0.1u l6 f.bead. c10 0.1u c28 0.1u r2 0 r7 15k l8 f.bead. c5 0.01u c1 1000p ax88172 u1 ax88172 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 vdd rst_type nc nc nc nc nc ana_xiq vdd clki testmode reset vss vdd pvdd pvss vc ptest xin12m xout12m vdd test0 test1 gpio0 gpio1 gpio2 phyrstn phyrstp vss nc atpgen led vdd speedup nc eecs eeck eedi eedo vss r1 avdd avss avss dp avss dm avss avdd extwakeupn nc nc vdd mdc mdio nc nc nc nc vss vdd col nc txclk crs txd0 txd1 txd2 txd3 txen vdd rxclk rxd0 rxd1 rxd2 rxd3 vdd rxer rxdv vss 4 1 23 j2 usb-con 4 1 3 2 gnd vdd5 d+ d- s s l4 f.bead. c13 0.47uf r3 10k l7 f.bead. c8 24p y1 12.000mhz c7 24p r5 220 r4 1m rx_clk rxd0 rxd2 txen txd0 /phy_rst gnd txd1 rxd1 tx_clk mdio vdd3 crs txd3 col rxdv txd2 rxer mdc rxd3 usb port link/act led option u3 : torex / xc74ul14aamr option 1 / nc : pin72 reset active high. dc 5.0v power 1206 & dip 1206 & dip 1206 & dip 1206 & dip 0 : pin72 reset active low. reset active low : used "r8" only. reset active high : used "u2" only. option 1206 & dip 1206 & dip avss and pvss : single-point ground option option (next version chip)
ax88172 usb to fast ethernet/homepna controller asix electronics corporation 23 rtl8201-ts6121a 2.1 ax88172 demo board b 22 friday, may 31, 2002 title size document number rev date: sheet of vdd3 vdd3 vdd3 tx+ tx- rx- rx+ led3 led2 led0 led1 x1 x2 avdd0 avdd1 avdd2 gnd gnd gnd x1 x2 mdio txd0 txd1 txd2 txd3 txen rxdv rxd0 rxd1 rxd2 rxd3 col crs rxer avdd2 dvdd0 avdd1 avdd0 vdd3 /phy_rst led0 led1 led3 led2 led4 led4 dvdd0 vdd3 vdd3 vdd3 vdd3 rxc txc mdc gnd r23 75 u7 ts6121a 1 2 3 6 7 8 9 10 11 14 15 16 1 2 3 6 7 89 10 11 14 15 16 c42 0.01u l10 f.bead. l12 f.bead. c50 0.1u r35 510 r38 510 r41 510 r16 2k 1% r19 1k r20 1k r40 4.7k r36 4.7k r34 4.7k d4 led d3 led r33 510 r31 510 r26 1k r25 1k r27 1k r29 1k r28 1k r32 4.7k r30 4.7k r15 2k r10 1.5k r14 20 r13 20 + c49 10uf/16v l9 f.bead. c44 0.1u c45 0.1u c43 0.1u rtl 8201 u6 rtl8201 25 26 27 6 5 4 3 2 7 22 21 32 36 48 29 35 45 20 19 18 16 1 23 24 46 47 9 10 12 13 15 8 14 11 17 30 31 28 33 34 43 40 39 38 37 41 44 42 mdc mdio rtt3/vctrl txd0 txd1 txd2 txd3 txen txc rxdv rxd0 avdd0 avdd1 avdd2 agnd agnd agnd rxd1 rxd2 rxd3 rxc col crs rxer x1 x2 led0/phya0 led1/phya1 led2/phya2 led3/phya3 led3/phya4 dvdd0 dvdd1 dgnd dgnd tprx- tprx+ rtset tptx- tptx+ isolate rept speed duplex ane ldps mii/snib resetb r37 1m r39 0 y2 crystal 25.000 mhz c52 20p r12 49.9 c51 20p c46 0.1u r24 75 c38 0.01u c47 0.1u j3 rj45 2 1 3 6 4 5 7 8 s s l11 f.bead. r22 75 r21 75 c39 0.01u d7 led c41 0.01u/2kv c48 0.1u c40 0.01u d5 led r18 49.9 d6 led r17 49.9 r11 49.9 vdd3 col txd1 rxd0 rxer rxd2 tx_clk mdio txen rxdv rxd3 txd0 rxd1 mdc crs txd3 txd2 rx_clk gnd /phy_rst set phy address to 00011 coll link led link 10-active link 100-active full led u6 : bothhand / ts6121a u5 realtek rtl8201 ( connect to chasis gnd ) 1206 & dip
ax88172 usb to fast ethernet/homepna controller asix electronics corporation 24 demonstration circuit b: ax88172 (ed3 version) + ethernet phy (8201lbl) ax88172 2.2 ax88172 demo board ed3 b 12 friday, october 04, 2002 title size document number rev date: sheet of vdd3 vdd3l vdd3l vdd3 vdd3l vdd5 gnd rxdv vdd3l rxer rxd2 rxd3 txd3 rxd0 vdd3l rxd1 rx_clk txen txd1 crs txd2 txd0 tx_clk vdd3l rst vdd3l mdio vdd3l mdc vdd3l col tx_clk mdio rx_clk txen txd0 rxer txd2 mdc col rxd0 vdd3 gnd rxd1 rxd3 rxd2 rxdv txd3 txd1 /phy_rst crs dplus eedo eecs eedi eeck vdd3l gnd gnd dminus gnd /phy_rst eedo eedi eeck eecs vdd3 led vdd3l rst avdd pvdd pvdd gnd gnd gnd avdd avdd vdd5 dplus dminus gnd pvss avss vdd3l avss pvss vdd3 vdd3 gnd gnd avss vdd3 avss avss c30 0.1u c31 0.1u c33 0.1u c36 0.1u + c19 47u/16v + c34 22u c18 0.01u l1 f.bead. c16 0.1u + c15 10u/16v u4 ams1117 3 2 1 vin vout adj/gnd c11 0.1u c2 0.1u c23 0.1u c26 0.1u l2 f.bead. c24 0.1u u1 93c56 1 2 3 4 5 6 7 8 cs sk di do gnd nc nc vcc c32 0.01u c28 0.1u c25 0.1u + c17 47u/16v c21 0.1u c22 0.1u c20 0.1u r11 0 c8 0.1u c3 0.1u r8 6.2k 1% c5 0.1u d1 led r1 1k + c29 22u c35 0.01u c10 0.1u l4 f.bead. c27 0.1u c9 0.1u r2 0 l6 f.bead. r9 15k c1 1000p c4 0.01u 4 1 23 j1 usb-con 4 1 3 2 gnd vdd5 d+ d- s s ax88172 u2 ax88172 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 vdd rst_type nc nc nc nc nc ana_xiq vdd clki testmode reset vss vdd pvdd pvss vc ptest xin12m xout12m vdd test0 test1 gpio0 gpio1 gpio2 phyrstn phyrstp vss nc atpgen led vdd speedup nc eecs eeck eedi eedo vss r1 avdd avss avss dp avss dm avss avdd extwakeupn nc nc vdd mdc mdio nc nc nc nc vss vdd col nc txclk crs txd0 txd1 txd2 txd3 txen vdd rxclk rxd0 rxd1 rxd2 rxd3 vdd rxer rxdv vss l5 f.bead. r3 10k c14 0.47uf c7 24p y1 12.000mhz c6 24p r6 1m r7 220 rx_clk rxd0 rxd2 txen txd0 /phy_rst gnd txd1 rxd1 tx_clk mdio vdd3 crs txd3 col rxdv txd2 rxer mdc rxd3 usb port link/act led 1206 & dip 1206 & dip 1206 & dip 1206 & dip 1206 & dip avss and pvss : single-point ground
ax88172 usb to fast ethernet/homepna controller asix electronics corporation 25 rtl8201bl mii1.0 2.2 rtl8201bl application circuit - interface with mac(mii) b 22 friday, december 20, 2002 title size document number rev date: sheet of vdd3 vdd3 vdd3 vdd3 gnd ch_gnd gnd gnd gnd gnd gnd gnd gnd gnd led2 led0 led3 led4 led1 x1 x2 vdd3 gnd gnd gnd vdd3 vdd3 led4/phyad4 led1/phyad1 gnd avdd3 vdd3 gnd gnd led3/phyad3 phy_rst avdd3 dvdd25 led0/phyad0 avdd25 led2/phyad2 dvdd25 x1 x2 txd0 txd1 txd2 txd3 txen col rxer txc mdc mdio rxc rxdv rxd3 rxd2 rxd1 rxd0 crs c42 0.01u/3kv r14 50 r23 75 c38 0.1u r21 75 r20 5.6k (1%) u5 rtl8201bl lqfp48 25 26 6 5 4 3 2 7 22 21 20 19 18 16 1 23 46 47 9 10 12 13 15 8 14 11 17 32 36 48 29 35 45 24 27 34 33 31 30 28 43 40 42 39 38 37 41 44 mdc mdio txd0 txd1 txd2 txd3 txen txc rxdv rxd0 rxd1 rxd2 rxd3 rxc col crs x1 x2 led0/phyad0 led1/phyad1 led2/phyad2 led3/phyad3 led4/phyad4 dvdd25 dvdd33 dgnd dgnd avdd25 avdd33 dvdd33 agnd agnd agnd rxer/fxen nc tptx+ tptx- tprx+ tprx- rtset isolate rptr resetb speed duplex ane ldps mii/snib/rtt3 c48 0.1u l8 bead c49 0.1u c45 22u c46 0.1u c47 0.1u l7 bead r19 50 c41 0.1u r18 50 r39 510 r43 510 r41 510 r42 4.7k r40 4.7k r38 4.7k d2 led d3 led r34 510 r37 510 r36 4.7k r32 4.7k r12 1.5k r17 2k r15 20 r16 20 r26 5.1k r25 5.1k c50 0.1u y2 crystal 25.000 mhz r35 0 r33 1m c43 20p c44 20p d6 led d4 led d5 led r30 5.1k r29 5.1k r28 5.1k r27 5.1k r31 5.1k u6 pe68515 1 2 3 15 14 16 7 5 6 11 12 10 rd+ rd- ct td- ct td+ rx+ ct rx- tx- cmt tx+ r13 50 c37 0.1u c39 0.1u c40 0.1u r22 75 u7 rj8-45 1 2 3 4 5 6 7 8 9 tx+ tx- rx+ n/c n/c rx- n/c n/c gnd r24 75 avdd25 avdd25 col txd1 rxer mdio txen txd0 mdc crs txd3 txd2 rx_clk tx_clk rxdv rxd0 rxd1 rxd3 rxd2 for emi supression (connect to chassis gnd) rtl8201bl has built in 3.3v to 2.5v regulator, and pin 8(avdd25) sources out 2.5v. a 22uf capacitir and a 0.1uf capacitor are recommended between avdd25 and gnd. place c14, c15, l4 close to avdd25 and place c11 close to dvdd25. u1/pin14 u1/pin48 place l2, c17, c18, c19 as close to each power pin as possible. hardwire configuration network: 1. this configuration shows enable: auto negotiation, full duplex, 100mbps, link down power saving, mii interface disable: isolate, repeater mode 2. these senven configuration pins could be connected to vdd or gnd directly. link 100-active full led coll set phy address to 00011 link 10-active link led rtl8201bl r18 value need fine tune, the range may from 2k to 5.6k
26 ax88172 preliminary remark: the schematic change between ed2 and ed3 are shown following: 1. 60mhz oscillator is no longer needed 2. ax88172 pin 23 need coonect to vbus in ed3 3. pin 70 (clki) changes from 60mhz osc to nc, 4. pin 71 (test mode) from vdd3l to nc.
27 ax88172 preliminary revisions history revision date comment v. 1.0 12/25/01 initial release v.1.1 12/28/01 pin 62 change from ?srom size to nc? r1 change from 6k +/-1% to 6.2k+/-1% power on reset specific 6ms ~10ms ?primary?phy id change to ?first? phy id in eeprom memory mapping v.1.2 2002/2/25 pin 62 change from ?nc? to ?rst_type? pin 72 change from ?reset? to?reset/reset? on page 12 modify following: usb vendor command modify from ?disable h/w mii operation? to ?software mii operation? usb vendor command modify from ?enable h/w mii operation? to ?hardware mii operation? read/write mointor mode at read bit 7-5 change from 100 to 101? add /reset timing reference design schematic updated bom update v.1.3 2002/5/7 chip ed2 new schematic with external 60 mhz add rtl 8201 bl version schematic remove bom v.1.4 2002/12/20 a dd ed3 reference design with rtl 8201bl version phy and remark the difference add 12m osc spec
28 ax88172 preliminary 4f, no.8, hsin ann rd., science-based industrial park, hsinchu, taiwan, r.o.c. tel: 886-3-5799500 fax: 886-3-5799558 email: support@asix.com.tw web: http://www.asix.com.tw

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